1. Field of the Invention
This invention relates generally to an improved direct contact structure for semiconductor devices and to a method of manufacturing therefor. The invention further relates to an improved capacitor structure having an increased value of capacitance as a function of surface area. The invention has particular applicability to semiconductor memory devices.
2. Description of the Background Art
Capacitors are widely used as passive elements which constitute integrated circuits in conventional semiconductor devices. As an example of a semiconductor device having such a capacitor, a sectional structure of a memory cell of a DRAM (Dynamic Random Access Memory) is shown in FIG. 10F. A memory cell of a DRAM includes a MOS (Metal Oxide Semiconductor) transistor and a capacitor.
Referring to FIG. 10F, a pair of n-type diffused layers 2a and 2b (the source and the drain) are formed on a surface of a p-type silicon substrate 1. A gate oxide film 3 is formed on the p-type silicon substrate 1 between the n-type diffused layers 2a and 2b. A gate electrode 4 is formed on the gate oxide film 3. The n-type diffused layers 2a and 2b, gate oxide film 3 and gate electrode 4 generally constitute a MOS transistor.
A silicon nitride layer 5 is formed on the n-type diffused layer 2b. The silicon nitride layer 5 serves as a capacitor gate insulating film. A capacitor gate electrode 6 is formed on a surface of the silicon nitride film 5. The n-type diffused layer 2b, silicon nitride film 5 and capacitor gate electrode 6 cooperatively constitute a capacitor of a memory cell.
A bit line 7 extends through a contact hole and is connected to the n-type diffused layer 2a. An element isolating oxide film 8 isolates each adjacent memory cells from each other.
Subsequently, a storing operation of the memory cell will be described. Referring to FIG. 10F, a voltage higher than a predetermined level is applied to the gate electrode 4 of the MOS transistor of the memory cell shown. Consequently, an n-type inversion layer is formed in a channel region 9 between the n-type diffused layer 2a serving as the source electrode and the other n-type diffused layer 2b serving as the drain electrode. Thus, electric charge moves from the bit line 7 to the n-type diffused layer 2b by way of the n-type diffused layer 2a and the inversion layer formed in the position of the channel region 9. The electric charge is then accumulated in surface portions of the capacitor gate electrode 6, silicon nitride layer 5 and n-type diffused layer 2b which cooperatively form a capacitor. The accumulated electric charge serves as stored data of information.
A storage function of memory cells of a DRAM depends upon judgment of presence or absence of electric charge accumulated in a capacitor of each memory cell. Accordingly, each capacitor is required to have a sufficient electric charge accumulating capacity to permit judgment of presence or absence of accumulation of electric charge. The capacity of a capacitor has a proportional relationship to an area of a capacitor gate insulating film which opposes the capacitor gate electrodes but has an inverse proportional relationship to the thickness of the film. In semiconductor devices for which a high integration is required in recent years, reduction of the area which is occupied in a plane by capacitors cannot be avoided. As such reduction proceeds, it has been attempted to make capacitor gate insulating film (dielectric films) from thin films in order to assure the capacities of capacitors. Also in the memory cell capacitors of the DRAM described above, each dielectric film is made from a thin film, and a silicon nitride film having a high dielectric constant is employed, by which the capacities of the capacitors are assured.
Subsequently, a process of producing a memory cell of such described above will be described with reference to FIGS. 10A to 10F.
At first, an element insulating film 8 is selectively formed on a surface of a p-type silicon substrate 1 as shown in FIG. 10A using the LOCOS (Local Oxidation of Silicon)) method.
Then, n-type impurity ion 11 is implanted into surface portion of the p-type silicon substrate 1 using a mask of patterned resist 10 to form an n-type diffused layer 2b as shown in FIG. 10B.
Subsequently, the resist 10 is removed, and a silicon nitride film 5 is deposited using the vacuum CVD (Chemical Vapor Deposition) method as shown in FIG. 10C.
An undesirable silicon oxide film 13 is formed on the main surface of the silicon substrate between the step of removing the resist and the step of forming a silicon nitride film 5. The undesirable silicon oxide film 13 causes problems as will be described later.
After that, polycrystalline silicon is deposited on a surface of the silicon nitride film 5, and the polycrystalline silicon film and the silicon nitride film 5 are patterned into a predetermined configuration as shown in FIG. 10D. By the step, a capacitor gate electrode 6 is formed.
Then, a gate oxide film 3 is formed on the surface of the p-type silicon substrate 1 by the thermal oxidation method as shown in FIG. 10E. A polycrystalline silicon layer is formed on a surface of the gate oxide layer 3. Then, the polycrystalline silicon layer and the gate oxide layer 3 are patterned into predetermined configuration. Subsequently, n-type impurity ion 11 is implanted into a surface portion of the p-type silicon substrate 1 using a thus patterned gate electrode 4 as a mask. By the step, n-type diffused layers 2a and 2b are formed on the surface of the p-type silicon substrate 1.
After that, an interlayer insulating film 12 is formed on the surface of the p-type silicon substrate 1 on which the MOS transistor and the capacitor are formed in this manner, as shown in FIG. 10F. A bit line 7 is further formed on a surface of the interlayer insulating film 12. The bit line 7 extends through a contact hole formed in the interlayer insulating film 12 and is connected to the n-type diffused layer 2a.
With a DRAM produced by such a producing process as described above, it is a problem that a silicon oxide film 13 is formed between the silicon nitride film 5 and the surface of the p-type silicon substrate 4 of the capacitor.
The problem with regard to undesirable silicon oxide film 13 will be described in the following. It is to be noted that the terminology of undesirable silicon oxide film here is used as a general name including an ambient produced oxide film described below and a chamber produced oxide film.
In the conventional producing process, the step of forming an n-type diffused layer 2b on a surface of a silicon substrate 1 (FIG. 10B) is performed using an ion implantation equipment or the like. The subsequent step of forming a silicon nitride film 5 on the surface of the silicon substrate 1 (FIG. 10C) is performed using a low pressure CVD equipment or the like. Between the two steps in the producing process, the silicon substrate 1 is transported between such two equipments. During such transportation, the silicon substrate 1 is exposed at the surface thereof to the external air. Consequently, an ambient produced oxide film is formed on the surface of the silicon substrate 1 by reaction with oxygen in the air. FIG. 14 illustrates a relationship between the thickness of such ambient produced oxide film and the interval of time over which the surface of the silicon substrate 1 is exposed to the external air. The ambient produced oxide film is formed in relatively short period to the thickness of about 10 .ANG., and thereafter, the speed of formation is reduced. Such ambient produced oxide film 13 is naturally formed normally with a thickness of 10 to 20 .ANG. or so.
Meanwhile, general structure of a low pressure CVD equipment is shown in FIG. 12. In the inside of such low pressure CVD equipment 14, a silicon nitride film 5 is formed on a surface of a p-type silicon substrate 1. The low pressure CVD equipment 14 includes a reactor tube 15, a reaction gas introducing section 16, and a vacuum discharging section 17. A heater 18 is provided on an outer periphery of the reactor tube 15.
The silicon substrate 1 is placed in the inside of the reactor tube 15, and formation of a film proceeds in the inside of the reactor tube 15. However, when the silicon substrate 1 is inserted into the inside of the reactor tube 15, the external air is admitted into the inside of the reactor tube 15. The thus admitted external air causes an oxide film to be formed on a surface of the silicon substrate 1 in the furnace heated to a temperature of 550.degree. to 650.degree. C. The oxide film is called contamination oxide film.
FIGS. 15 and 16 illustrate the thickness of such contamination oxide film. In particular, FIG. 15 illustrates a relationship between the interval of time for which the silicon film is maintained in the reactor tube 15 and the thickness of the contamination oxide film thus formed, using various types of reactor furnace as a parameter. Meanwhile, FIG. 16 illustrates a relationship between the temperature at which the silicon film 1 is processed in the reactor furnace and the thickness of the contamination oxide film, using an interval of time for which the silicon film is maintained as a parameter.
In this manner, with the conventional process of producing memory cells of a DRAM, such silicon oxide film 13 is formed between the silicon nitride film 5 of the capacitor and the surface of the p-type silicon substrate 1. Consequently, the dielectric layer of the capacitor has a multi-layer film structure having the silicon oxide layer 13 and the silicon nitride film 5. FIG. 11 shows a transmission scanning electron microscope photograph of a section of an exemplary capacitor having a multi-layer film structure. Referring to FIG. 11, formation of the silicon oxide film 13 can be clearly seen. It is to be noted that the photograph exhibits a capacitor of a two-layer film structure, as a dielectric film, having a silicon nitride film (Si.sub.3 N.sub.4) and a top silicon oxide film (top SiO.sub.2) formed on the silicon nitride film. On the other hand, FIG. 13 shows an analytic view in the multi-layer film wherein the multi-layer film is analyzed by the Auger electron analysis which is a method of microanalysis. In FIG. 13, N denotes nitrogen, Si silicon and O oxygen. Then, as seen in FIG. 13, a silicon oxide film 13 (natural oxide film and contamination oxide film) exists between the silicon oxide film 5 and the silicon substrate 1.
Subsequently, description will be given of the fact that a capacitor of a multi-layer film structure having the silicon nitride film 5 and the silicon oxide film 13 has a smaller capacity than a capacitor which only has a silicon nitride film. It is assumed here that the ratio in dielectric constant between the silicon nitride film and the silicon oxide film is 2:1. In this instance, if the thickness of the silicon nitride film is 60 .ANG., then the film thickness corresponds to 30 .ANG. where it is converted into a thickness of a silicon oxide film which has an equivalent capacity. However, in the case of the multi-layer film structure, if the thickness of the silicon nitride film is 60 .ANG. and the thickness of the silicon oxide film 10 .ANG., the thickness of a silicon oxide film having an equivalent capacity is 40 .ANG.. The electric charge accumulating capacity of a capacitor increases as the thickness of a dielectric layer decreases. Accordingly, the multi-layer film structure having a silicon nitride film and a silicon oxide film has a small electric charge accumulating capacity comparing with a capacitor of a single-layer film structure only having a silicon nitride film. Meanwhile, a natural oxide film or a contamination oxide film is not formed intentionally. Accordingly, the conventional process of production has a problem that a capacitor actually produced has a smaller capacity than an intended electric charge accumulating capacity.
A problem derived from the formation of the undesirable silicon oxide film is generated also in connection with the direct contact structure between the silicon substrate and a conductive layer. FIG. 17 schematically shows the direct contact structure. The contact structure between the bit line 7 and the n type impurity region 2a shown in FIG. 10F corresponds to such a structure, for instance. Referring to FIG. 17, an impurity region 52 is formed on the main surface of the silicon substrate 1. A contact hole 53 reaching the impurity region 52 is formed in the insulating layer 50 formed on the main surface of the silicon substrate 1. A conductive layer 51 is connected to the impurity region 52 through the contact hole 54. A polycrystalline silicon layer doped with impurities, an Al layer, an Al alloy layer or the like is used as the conductive layer 51. The undesirable silicon oxide film 13 is incidentally formed between the surface of the impurity region 52 and the conductive layer 51. The undesirable silicon oxide film 13 is consisted of an ambient produced oxide film and a chamber produced oxide film, as in the above described example of the capacitor. If the conductive layer 51 is formed of an Al alloy or an alloy of metal having high melting point, the layer is formed by sputtering. Since the temperature for forming the film is low in sputtering, the surface of the substrate is not oxidized by the remaining oxide. Therefore, there is no chamber produced oxide film. If the conductive layer 51 is of polycrystalline silicon or a metal having high melting point which is formed by reduced pressure CVD method, the temperature of film formation is as high as 550.degree. C. or more. Therefore, the surface of the substrate is oxidized by the remaining oxide. Consequently, a chamber produced oxide film having the thickness of about 20 to 30 .ANG. is formed.
Since the undesirable silicon oxide film is of high resistance, it increases the contact resistance between the conductive layer 51 and the impurity region 2a.
The deterioration of the contact characteristics caused by a high resistance oxide film formed on the contact interface is common to a contact structure between a polycrystalline silicon interconnection layer and a layer of Al alloy or of a metal having high melting point, and to a contact structure between layers of Al alloy.
The following methods have been known for removing the undesirable silicon oxide film.
If the conductive layer 51 is formed of an Al alloy or an alloy of metal having high melting point which is formed by sputtering, the silicon substrate 1 on which the ambient oxide film 13 is generated is introduced in a sputtering apparatus, and the ambient oxide film 13 is removed by sputter etching. Thereafter, a film of Al alloy or metal having high melting point is formed by sputtering in the same apparatus.
If the conductive layer 51 is of polycrystalline silicon or metal having high melting point formed by reduced pressure CVD method, a polycrystalline silicon layer 51 is formed at first in a reduced pressure CVD apparatus. Thereafter, ion implantation is carried out on the undesirable silicon oxide film 13 consisted of the ambient produced oxide film and the chamber produced oxide film generated during formation of the polycrystalline silicon layer 51. The undesirable silicon oxide film is destroyed by the ion implantation, and the interface between the polycrystalline silicon layer 51 and the impurity region 52 is activated to reduce the resistance thereof.
If the conductive layer is of polycrystalline silicon, another method of removing is as follows. Namely, the temperature of a reaction furnace of the reduced pressure CVD apparatus is lowered to be not more than 400.degree. C., and the silicon substrate 1 is introduced in the reaction furnace. By doing so, possible oxidation caused by the air unavoidably introduced to the reaction furnace is prevented. Thereafter, the chamber is evacuated, and the temperature is increased to a prescribed value to form the polycrystalline silicon layer 51. In accordance with this method, formation of the chamber produced oxide film can be prevented. However, the ambient produced oxide film is left as it is.